如果一個(gè)程序中,有兩個(gè)中斷,假若為CAP1中斷和CAP2中斷,我查到DSP默認(rèn)的優(yōu)先級(jí)是CAP2級(jí)別高于CAP1,
是不是當(dāng)CAP2滿足中斷條件后,CAP2進(jìn)入中斷,即使此刻CAP1也滿足中斷條件,也不會(huì)進(jìn)入CAP1中斷??
還有就是如果自始至終,CAP1和CAP2都滿足中斷條件的話,CAP1就會(huì)一直進(jìn)不去中斷??
我在實(shí)際測(cè)量中發(fā)現(xiàn),分別用兩個(gè)信號(hào)發(fā)生器 都產(chǎn)生兩個(gè)50hz的 高低電平信號(hào),幅值滿足DSP能夠進(jìn)入中斷的要求。
測(cè)試中發(fā)現(xiàn),當(dāng)僅有CAP1中斷時(shí),可以正常捕獲數(shù)值,CAP1的兩個(gè)寄存器差值為50HZ對(duì)應(yīng)數(shù)字量,當(dāng)僅有CAP2中斷時(shí),也可以正常捕獲數(shù)值,CAP2的兩個(gè)寄存器差值與CAP1基本差別不大。由此可以確定兩個(gè)CAP中斷沒有問題。
但是,當(dāng)CAP1和CAP2同時(shí)滿足中斷條件時(shí),根據(jù)程序單步運(yùn)行發(fā)現(xiàn),兩個(gè)中斷也都能進(jìn)入,但是捕獲數(shù)值不正確。此時(shí)CAP1和CAP2的兩個(gè)寄存器雖然數(shù)值時(shí)刻在變化,但是差值始終為0,一直弄不清原因,求救中...............
主要程序如下:
#include "DSP280x_Device.h" // DSP280x Headerfile Include File
#include "DSP280x_Examples.h" // DSP280x Examples Include File
interrupt void ecap1_isr(void);
interrupt void ecap2_isr(void);
void InitECapture(void);
void Fail(void);
// Global variables used in this example
Uint32 ECap1IntCount;
Uint32 ECap2IntCount;
Uint32 TSt1;
Uint32 TSt2;
Uint32 TSt3;
Uint32 TSt4;
Uint32 Period1;
Uint32 Period2;
void main(void)
{
InitSysCtrl();
InitECap1Gpio();
InitECap2Gpio();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.ECAP1_INT = &ecap1_isr;
PieVectTable.ECAP2_INT = &ecap2_isr;
EDIS;
InitECapture();
ECap1IntCount = 0;
ECap2IntCount = 0;
IER |= M_INT4;
PieCtrlRegs.PIEIER4.bit.INTx1 = 1;
PieCtrlRegs.PIEIER4.bit.INTx2 = 1;
EINT;
ERTM;
for(;;)
{
asm(" NOP");
}
}
void InitECapture()
{
ECap1Regs.ECEINT.all = 0x0000;
ECap1Regs.ECCLR.all = 0xFFFF;
ECap1Regs.ECCTL1.bit.CAPLDEN = 0;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = 0;
ECap1Regs.ECCTL2.bit.CONT_ONESHT = 1;
ECap1Regs.ECCTL2.bit.STOP_WRAP = 3;
ECap1Regs.ECCTL1.bit.CAP1POL = 1;
ECap1Regs.ECCTL1.bit.CAP2POL = 1;
ECap1Regs.ECCTL1.bit.CAP3POL = 1;
ECap1Regs.ECCTL1.bit.CAP4POL = 1;
ECap1Regs.ECCTL1.bit.CTRRST1 = 0;
ECap1Regs.ECCTL1.bit.CTRRST2 = 0;
ECap1Regs.ECCTL1.bit.CTRRST3 = 0;
ECap1Regs.ECCTL1.bit.CTRRST4 = 0;
ECap1Regs.ECCTL2.bit.SYNCI_EN = 0;
ECap1Regs.ECCTL2.bit.SYNCO_SEL = 2;
ECap1Regs.ECCTL1.bit.CAPLDEN = 1;
ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1;
ECap1Regs.ECCTL2.bit.REARM = 1;
ECap1Regs.ECCTL1.bit.CAPLDEN = 1;
ECap1Regs.ECEINT.bit.CEVT4 = 1;
ECap2Regs.ECEINT.all = 0x0000;
ECap2Regs.ECCLR.all = 0xFFFF;
ECap2Regs.ECCTL1.bit.CAPLDEN = 0;
ECap2Regs.ECCTL2.bit.TSCTRSTOP = 0;
ECap2Regs.ECCTL2.bit.CONT_ONESHT = 1;
ECap2Regs.ECCTL2.bit.STOP_WRAP = 3;
ECap2Regs.ECCTL1.bit.CAP1POL = 1;
ECap2Regs.ECCTL1.bit.CAP2POL = 1;
ECap2Regs.ECCTL1.bit.CAP3POL = 1;
ECap2Regs.ECCTL1.bit.CAP4POL = 1;
ECap2Regs.ECCTL1.bit.CTRRST1 = 0;
ECap2Regs.ECCTL1.bit.CTRRST2 = 0;
ECap2Regs.ECCTL1.bit.CTRRST3 = 0;
ECap2Regs.ECCTL1.bit.CTRRST4 = 0;
ECap2Regs.ECCTL2.bit.SYNCI_EN = 0;
ECap2Regs.ECCTL2.bit.SYNCO_SEL = 2;
ECap2Regs.ECCTL1.bit.CAPLDEN = 1;
ECap2Regs.ECCTL2.bit.TSCTRSTOP = 1;
ECap2Regs.ECCTL2.bit.REARM = 1;
ECap2Regs.ECCTL1.bit.CAPLDEN = 1;
ECap2Regs.ECEINT.bit.CEVT4 = 1;
}
interrupt void ecap1_isr(void)
{
TSt1 = ECap1Regs.CAP1;
TSt2 = ECap1Regs.CAP2;
Period1 = TSt2-TSt1;
ECap1IntCount++;
ECap1Regs.ECCLR.bit.CEVT4= 1;
ECap1Regs.ECCLR.bit.INT = 1;
ECap1Regs.ECCTL2.bit.REARM = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
}
interrupt void ecap2_isr(void)
{
TSt3 = ECap2Regs.CAP1;
TSt4 = ECap2Regs.CAP2;
Period2 = TSt4-TSt3;
ECap2IntCount++;
Period4=abs(TSt3-TSt1);
ECap2Regs.ECCLR.bit.CEVT4 = 1;
ECap2Regs.ECCLR.bit.INT = 1;
ECap2Regs.ECCTL2.bit.REARM = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP4;
}
void Fail()
{
asm(" ESTOP0");
}
//===========================================================================
// No more.
//===========================================================================
【問】2806 CAP和中斷
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@zhanghuawei
[圖片]我只能頂起這個(gè)問題,請(qǐng)版主去回答!貢獻(xiàn)自己一點(diǎn)力量啦
仁兄,這問題太專業(yè),磚家全被你嚇跑了。
頂一下,答這顆芯片是F2803x的升級(jí)版本,增加了RAM, Flash,主頻, CAP和HCAP的數(shù)量,PWM通道的數(shù)量,QEP的數(shù)量,80pin和100pin兩種,可以提供雙邊緣調(diào)頻控制。內(nèi)部還增加了10 位基準(zhǔn)的模擬比較器,并可直接對(duì)其進(jìn)行路由以控制 PWM 輸出。設(shè)計(jì)時(shí)參考F2803X,這IC資料比較多
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